This application is based upon and claims priority from prior French Patent Application No. 0104437, filed Apr. 2, 2001, the disclosure of which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention generally relates to the field of integrated circuits and more particularly to vertical insulated gate transistors.
The invention applies in particular, although not exclusively, to high-speed logic circuits and radio-frequency circuits. More generally, the invention finds an application in technologies below 0.07 micron.
2. Description of Related Art
The vertical transistor is a device that overcomes the limitations of the planar MOS transistor, in lengths less than 0.1 micron. Its conduction body consists of a silicon pillar insulated and covered by a gate. It therefore has at least two conduction interfaces. Accordingly, the current Ion and the transconductance per unit width are interfaces. Accordingly, the current Ion and the transconductance per unit width are at least doubled. For sufficiently fine silicon pillars, with a dimension of the order of 50 nm, coupling between the gates is observed, reducing the effects of the short channels. This makes it possible to reduce the doping of the pillar, which is particularly favorable from the point of view of the current Ion. Also, conduction over a plurality of interfaces, in conjunction with the coupling of the gates, makes it possible to eliminate the need to form ultrafine gate oxides or high-permittivity dielectrics.
What is more, the vertical transistor is a technological platform particularly suitable for implementing a coating gate architecture with ultrashort dimensions. This is because the channel length in the vertical transistor is not fixed by the photolithographic resolution. It is therefore possible to form channels with very small dimensions using standard photolithographic equipment. Also, coating a projecting silicon pillar with a gate is much simpler than coating a thin silicon film buried in a substrate.
The person skilled in the art knows of many methods of fabricating a vertical insulated gate transistor, using different techniques to form the silicon pillar. In a first approach, the silicon pillar is etched anisotropically from a silicon layer grown epitaxially from the isolated substrate.
In a second, more sophisticated approach, the pillar is grown epitaxially, overflowing into an open window in a dielectric layer.
The first approach draws its inspiration largely from steps of the conventional method of producing a planar transistor. In particular, forming the pillar by etching resembles etching the gate of a planar transistor. The pillar is doped after it is formed, although it could be doped during epitaxial growth or before etching. The source and drain regions are implanted in a self-aligned manner relative to the pillar. The source can also be implanted before epitaxial growth, in which case it is referred to as xe2x80x9ccontinuousxe2x80x9d (the source areas on either side of the pillar are joined together). The gate oxide is then formed on the flanks of the silicon pillar. The polysilicon gate is then deposited, doped and then etched.
This kind of approach, which is simple to implement, makes it possible to develop a CMOS line based on vertical transistors at reduced cost.
With the second approach, the epitaxially grown pillar is planarized by mechanical/chemical polishing. The benefit of the second approach is that it leaves at the base of the pillar a thick dielectric reducing the capacitance of the overlap on the source.
Although these two approaches are useful, they are not without their shortcomings. One shortcoming with these two approaches is that the thickness of the silicon pillar depends on the resolution of the photolithographic method used either to etch the pillar directly or to open the window in the dielectric layer. Thus at present there is no hope of producing very thin pillars (i.e. thinner than 50 nm) with conventional photolithography, which consequently limits the effectiveness of the gate coupling phenomenon.
Another shortcoming with these two approaches is that in a vertical transistor, the depth of the junctions is equal to the thickness of the silicon pillar. For a relatively thick pillar, the junction depth can therefore be very large compared to the length of the channel, which is extremely unfavorable in terms of controlling the effects of short channels.
Accordingly, a need exist to overcome these shortcomings.
The present invention decorrelates the thickness of the pillar of the vertical transistor from the photolithographic resolution, i.e. to define the thickness of the channel independently of the photolithographic resolution.
Moreover, the present invention provides a vertical transistor with four conduction channels.
Furthermore, the present invention is to reduce the depth of the source and drain extension areas independently of the depth of the junctions.
Accordingly, in one embodiment, a silicon-germanium alloy layer is interleaved into the stack of the pillar, further silicon is grown epitaxially around the pillar, and the core of the pillar, which is of silicon-germanium alloy, is then emptied out by etching which is selective with respect to the silicon and to an oxide layer. This produces two very thin xe2x80x9cconnectingxe2x80x9d semiconductor areas that can be isolated and coated with a gate. The source and drain regions can be diffused into these very thin semiconductor areas, which forms very shallow extension areas. The final device then has four conduction channels operating over these two connecting semiconductor areas, which are entirely impoverished.
It should also be noted that the invention applies regardless of the approach adopted to forming the pillar, i.e. anisotropic etching or epitaxial growth in an open window in a dielectric block.
More generally, the invention proposes a method of fabricating a vertical insulated gate transistor, including forming a vertical semiconductor pillar on a semiconductor substrate and forming a dielectrically isolated semiconductor gate resting on the flanks of the pillar and on the top surface of the substrate.
Furthermore, forming the pillar includes forming a primary semiconductor pillar resting on the substrate and forming a cavity in the primary pillar, and in that forming the insulated gate further includes coating the internal walls of the cavity with an isolating dielectric material and filling the cavity thus isolated with the gate material, to form between the portion of the insulated gate situated in the cavity and the portion of the insulated gate resting on the flanks of the pillar two connecting semiconductor regions extending between the source and drain regions of the transistor. As previously indicated, these two connecting semiconductor regions will support the four conduction channels.
In one embodiment of the invention forming the primary pillar includes:
forming a stack including a first layer of a first semiconductor material, for example silicon, a second layer of a second semiconductor material, for example a silicon-germanium alloy (possibly a silicon-germanium-carbon alloy), that can be selectively eliminated with respect to the first material, and a third layer of the first material, and
forming on the stack a surface semiconductor layer of the first material (it is this surface layer that will define the thickness of the connecting semiconductor regions),
and the second layer of the stack is etched selectively to form said cavity. As indicated above, the invention is compatible with producing the pillar by anisotropic etching or by epitaxial growth in a dielectric window.
More particularly, with this latter approach, the stack is formed by selective epitaxial growth inside a window formed in a dielectric block resting on the top surface of the substrate, said window opening onto the top surface of the substrate. Forming the surface semiconductor layer includes removing the dielectric block and selective epitaxial growth of said surface layer on said stack.
In a different embodiment of the invention forming the stack of the primary pillar includes epitaxial growth of said three layers on the top surface of the substrate followed by anisotropic etching of the epitaxially grown layers. Forming the surface semiconductor layer then includes selective epitaxial growth of said surface layer on said stack thus formed.
In one embodiment of the invention forming the insulated gate includes forming an external isolating layer on the primary pillar and an internal isolating layer on the internal walls of the cavity, depositing a gate material on the external isolating layer and in the coated cavity of the internal isolating layer, and anisotropically etching the gate material.
The thickness of the surface layer can be of the order of a few tens of nanometers, for example 20 nanometers.
The method advantageously includes annealing to activate dopants of the source and drain regions leading by exodiffusion to the formation of source and drain extension areas in a portion of the semiconductor connecting regions.
The invention also provides an integrated circuit including an insulated gate vertical transistor including, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer.
According to one general feature of the invention the other of the source and drain regions is in the bottom part of the pillar and the insulated gate includes an isolated external portion resting on the flanks of the pillar and an isolated internal portion situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions extending between the source and drain regions. The thickness of each semiconductor region can be of the order of a few tens of nanometers, for example 20 nanometers.
In one embodiment of the invention each connecting semiconductor region incorporates source and drain extension areas.